Intel
An 80-Tile 1.28TFLOPS Network-on-Chip in 65nm CMOS
A 275mm2 network-on-chip architecture contains 80 tiles arranged as a 10×8 2D array
of floating-point cores and packet-switched routers, operating at 4GHz. The 15-FO4
design employs mesochronous clocking, fine-grained clock gating, dynamic sleep
transistors, and body-bias techniques. The 65nm 100M transistor die is designed to
achieve a peak performance of 1.0TFLOPS at 1V while dissipating 98W.
Implementation of the 65nm Dual-Core 64b Merom Processor
Merom is a dual-core 64b processor implementing the CoreTM architecture. The 143mm2
die has 291M transistors in a 65nm 8M process. The shared 4MB 16-way L2 cache
uses PMOS power gating to minimize leakage. The processor operates in a wide core
frequency range of 1 to 3GHz, a bus frequency range of 666 to 1333MHz and voltage
range of 0.85 to 1.325V, while providing 40% better power performance.
IBM
Design of the POWER6™ Microprocessor
The POWER6™ microprocessor combines ultra-high frequency operation, aggressive
power reduction, a highly scalable memory subsystem, and mainframe-like reliability,
availability, and serviceability. The 341mm2 700M transistor dual-core microprocessor
is fabricated in a 65nm SOI process with 10 levels of low-k copper interconnect. It
operates at clock frequencies over 5GHz in high-performance applications, and
consumes under 100W in power-sensitive applications.
A Distributed Critical-Path Timing Monitor for a 65nm High-Performance
Microprocessor
A distributed critical-path timing monitor (CPM) is designed as part of the POWER6TM
microprocessor in 65nm SOI. The CPM is capable of monitoring timing margin, process
variation, localized noise and VDD droop, or clock stability. It tracks critical-path delay to
within 3 FO2 delays at extreme operating voltages with a standard deviation less than
1/2 an FO2 delay. The CPM detects DC VDD droops greater than 10mV and tracks timing
changes greater than 1 FO2 delay.
AMD
An Integrated Quad-Core OpteronTM Processor
An integrated quad-core x86 processor is implemented in a 65nm 11M SOI CMOS
process. Based on an enhanced OpteronTM core, the SoC-developed processor employs
power- and thermal-management techniques throughout the design. The SRAM cache
designs target process variation considerations and future process scalability. A
DDR2/DDR3 combo-PHY and HT3 I/Os provide high-bandwidth interfaces.
SONY/Toshiba/IBM
Implementation of the CELL Broadband Engine™ in a 65nm SOI Technology
Featuring Dual-Supply SRAM Arrays Supporting 6GHz at 1.3V
The 65nm CELL Broadband Engine™ design features a dual power supply, which
enhances SRAM stability and performance using an elevated array-specific power
supply, while reducing the logic power consumption. Hardware measurements
demonstrate low-voltage operation and reduced scatter of the minimum operating
voltage. The chip operates at 6GHz at 1.3V and is fabricated in a 65nm CMOS SOI
technology.
Sun
An 8-Core 64-Thread 64b Power-Efficient SPARC SoC
The 8-core 64-thread 64b power-efficient 2nd-generation Niagara SPARC SoC has 4MB
L2 cache with one x8 PCI-Express, two 10G Ethernet (XAUI), and 8 FBDIMM ports. The
on-chip SerDes provide greater than 1Tb/s bandwidth. The 500M transistor chip with a
die size of 342mm2 is implemented in a 11M 65nm triple-Vt CMOS process
